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HLDVT provides a unique forum for industrial practitioners and
researchers in test and verification to interact, exchange ideas and
discuss directions and trends.
We look forward to an excellent program that features an interesting
mix of papers on test generation, assertions, test,
transformation-based verification, SAT, and system-level modeling. In
addition to the submitted papers, the program includes invited papers
in special sessions on "Industrial Trends in Test and Validation" and"Advances in Hybrid Verification." The traditional HLDVT panel
discussion will consider the timely topic of "Assertion-Based
Verification." J. Scott Runner of Qualcomm will deliver the keynote at
the conference banquet. He will speak on the challenges of
verification efficiency.
Important dates:
Early Registration Deadline: October 19, 2006
Pre-Conference Registration Deadline: November 3, 2006
(Registration also available at conference)
Hotel Registration Deadline: October 23, 2006
The advance program, hotel
information, and registration links are available on the HLDVT'06 web
pages at: http://www.hldvt.com/06.
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Wednesday -- Thursday -- Friday
| |
| 6:00
pm - 8:00 pm |
Registration |
| |
| 7:00
am - 8:00 am |
Continental
Breakfast |
| 7:00
am - 5:00 pm |
Registration |
| 8:00
am - 8:10 am |
Welcome Remarks |
| 8:10
am - 9:25 am |
Session
1: Test Case Generation I
DVGen:
Increasing Coverage by Automatically Combining Test Specifications
K. D. Rich, R. Shaw, S. G. Govindaraju, D. Dobrikin, Transmeta
Corp.
Test
Directive Generation for Functional Coverage Closure Using Inductive
Logic Programming
H.- W. Hsueh, K. Eder, U. of Bristol
Automated
Coverage Directed Test Generation Using Cell-Based Genetic Algorithm
A. Samarah, A. Habibi, S. Tahar, Concordia U |
| 9:25
am - 9:45 am |
Break |
| 9:45
am - 11:00 am |
Session
2: Special Session I
Disjunctive
Transition Relation Decomposition for Efficient Reachability Analysis
S. Stergiou, Stanford U
J. Jain, Fujitsu Labs
Trends
in Test: Challenges and Techniques
W. Meyer, Synopsys
Formal
Verifications in Modern Chip Designs
K.-Y. Khoo, Cadence |
| 11:00
am - 11:20 am |
Break |
| 11:20
am - 12:25 pm |
Session
3: Testing and Design for Testability
DFT
and Probabilistic Testability Analysis at RTL
J. M. Fernandes, M. Santos, A. Oliveira, J. P. Teixeira, IST/INESC-ID
Easily
Testable Implementation for Bit Parallel Multipliers Over GF (
2^ m)
H. Rahaman, J. Mathew, A. Jabir, D. K. Pradhan, U. Bristol
Error
Detection Using Model Checking vs. Simulation
S. Verma, P. Lee, I. Harris, U California, Irvine |
| 12:25
pm - 2:00 pm |
Lunch |
| 2:00
pm - 3:40 pm |
Session
4: Assertions and Transactions
Assertion-based Verification of Behavioral
Descriptions with Non-linear Solver
I. Ugarte, P. Sanchez, U. Cantabria
Efficient
Automata-Based Assertion-Checker Synthesis of PSL Properties
M. Boule, Z. Zilic, McGill U
Specification
Language for Transaction Level Assertions
W. Echer, V. Esen, M. Hull, T. Steininger, M. Velten, Infineon
On the
Automatic Transactor Generation for the TLM-based Design Flow
N. Bombieri, F. Fummi, U. Verona |
| 3:40
pm - 4:00 |
Break |
| 4:00
pm - 5:40 pm |
Session
5: Test Case Generation II
Addressing
Test Generation Challenges for Configurable Processor Verification
S. Johnson, D. Jani, Tensilica
M. Rimon, Y. Lichtenstein, A. Adir, I. Jaeger, M. Vinov, IBM
DeepTrans
- Extending the Model-based Approach to Functional Verification
of Address Translation Mechanisms
A. Koyfman, Y. Katz, A. Adir, L. Fournier, IBM
CP with
Architectural State Lookup for Functional Test Generation
B. Gutkovich,
A. Moss, Intel
Reusable
On-Chip System Level Verification for Simulation Emulation and
Silicon
A. Maman, S. Goldschlager, H. Miller, D. Bell, R. Slater, O. Ben-Moshe,
N. Levi,
H. Gilboa, Freescale |
| 6:00
pm - 8:00 pm |
Dinner Banquet |
| |
Keynote:
J. Scott Runner, Qualcomm
"Time to Quality: The Challenge of Verification Efficiency" |
| |
| 7:00
am - 12:00 pm |
Registration |
| 7:00
am - 8:00 am |
Continental
Breakfast |
| 8:00
am - 9:05 am |
Session
6: Transformation-based Verification Transaction
Routing and its Verification by Correct Model Transformations
S. Abdi, D. Gajski, U California, Irvine
Taming
the Complexity of STE-based Design Verification Using Program
Slicing
V. Vedula, F. Andersen, J. Abraham, U Texas, Austin
MMV:
Metamodeling Based Microprocessor Validation Environment
A. T. Dingankar, Intel, D. Mathaikutty, S. Shukla, Virginia Tech,
S. Kodakara, D. Lilja, U. Minnesota |
| 9:05
am - 9:25 am |
Break |
| 9:25
am - 10:40 am |
Session
7: Special Session II: Hybrid Verification, Survey and Latest Results
Distance-Guided
Hybrid Verification with GUIDO
V. Bertacco, U Michigan
EverLost:
A Flexible Platform for Industrial-Strength Abstraction-Guided
Simulation
A. Hu, U British Columbia
Semi-Formal
Verification at IBM
J. Baumgartner, IBM |
| 10:40
am - 11:00 am |
Break |
| 11:00
am - 12:30 pm |
Session
8: SAT and Equivalence Verification
Guiding
CNF-SAT Search by Analyzing Constraint-Variable Dependencies and
Clause Lengths
V. Durairaj, P. Kalla, U Utah
Equivalence
Checking with Rule-Based Equivalence Propagation and High-Level
Synthesis
T. Nishihara, T. Matsumoto, M. Fujita, U Tokyo
Practical
Issues in Sequential Equivalence Checking through Alignability:
Handling Don't Cares and Generating Debug Traces
I.-H. Moon, P. Bjesse, C. Pixley, Synopsys
IChecker:
An Efficient Checker for Inductive Invariants
F. Lu, T. Cheng, U California, Santa-Barbara |
| 12:30 pm -
2:00 pm |
Lunch |
| 2:00 pm -
3:30 pm |
Session
9: Panel: Assertion-Based Verification - What is the Big Deal?
Organizer:
S. Shukla
Moderator: A. Hu
Panelists: C. Pixley, J. Abraham, H. Foster, P. Ashar, A. Landver
|
| 3:30
pm - 3:50 pm |
Break |
| 3:50
pm - 5:20 pm |
Session
10: System Level View and Modeling Runtime
Deadlock Analysis of SystemC Design
E. Cheung, P. Satapathy, V. Pham, H. Hsieh, U California, Riverside
X. Chen, Novas
Extracting
a simplified view of design functionality via vector simulation
O. Guzey, C. H.-P. Wen, L.-C. Wang, U California, Santa-Barbara
T. Feng, Cadence, M. Abadir, Freescale
A Tool
for Automatic Detection of Deadlock in Wormhole Networks on Chip
S. Taktak, J.-L. Desbarbieux, U Paris 6
E. Encrenaz, ENS Cachan & CNRS
Polychronous
Methodology for System Design: A True Concurrency Approach
S. Suhaib, D. Mathaikutty, S. Shukla, Virginia Tech
J.-P. Talpin, INRIA |
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